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STLC1502

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7.8 GPIO/Keypad encoder

The GPIO block is available as a cell that controls 20 input/output pins. The block includes a key scanning

encoder. The encoder function is an alternative to the use of 12 I/O pins. The 12 pins are organized as a

6X6 matrix providing an interface to a 36 key keyboard. 16 pins are also multiplexed with the HPI external

interface. The HPI interface is selected by external pin HPISEL. Two pins GPIO18, GPIO19 are direct in-

terrupt sources in the interrupt register when programmed as inputs.

The pin description of the GPIO pins can be found in the Pin Description Table in Section 4.1.

7.8.1 GPIO operation mode

The GPIO operation mode is the Parallel Port mode.

Each of the 20 signals may be programmed as an input or an output through a set up register. Once pro-

grammed, each pin maintains its identity as an input or output. Voltages are standard process port levels,

0 and 3.3 volts. The on chip ARM processor may read or write to the port at any time.

7.8.2 Keyboard operation mode

The keyboard may contain up to 36 keys. Twelve (12) port pins provide a 6x6 scanning matrix. Six of the

pins are strobes and six of the pins are inputs. The application circuitry will provide small series resistors

to prevent electrostatic damage to the port pins.

The circuitry will scan the keys at a rate of 10, 20, 40 or 80 msecs, controlled by the software. Two suc-

cessive cycles are needed to validate a key. Only one key will be allowed down in a scan cycle. Once

validated as being down, the "no key down" condition must be validated for two complete cycles when the

key is released.

Every valid key condition will cause the value of the key to be written to a register and

an interrupt shall be set. Two key rollover will not be supported unless the solution is easier to implement

than the method described above.

7.8.4 GPIO registers map [0x0C400000]

The base address of GPIO registers is 0x0C400000.

The offset of any particular register from the base address is the following.

UART_regBase+ 0x20

ASCTxReset

Flush Transmit buffer (Fifo)

UART_regBase+ 0x24

ASCRxReset

Flush Receive buffer (Fifo)

Address

Name

R/W

Notes

GPIO_regBase+ 0x00

Control

R/W

This register allows to set the

block functionality

GPIO_regBase+ 0x04

Mask

This register allows GPIO direc-

tion setting (output enable)

Address

R/W

Notes

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