H8SLASH3021 datasheet(53/712 Pages) RENESAS

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2. CPU

Rev.2.00 Mar. 22, 2007 Page 29 of 684

REJ09B0352-0200

2.6.3

Tables of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation

used in these tables is defined as follows.

Operation Notation

General register (destination)*

General register (source)*

General register*

ERn

General register (32-bit register or address register)

(EAd)

Destination operand

(EAs)

Source operand

CCR

Condition code register

N (negative) flag of CCR

Z (zero) flag of CCR

V (overflow) flag of CCR

C (carry) flag of CCR

Program counter

Stack pointer

#IMM

Immediate data

disp

Displacement

Addition

–

Subtraction

Multiplication

Division

∧

Logical AND

∨

Logical OR

⊕

Exclusive logical OR

→

Move

NOT (logical complement)

:3/:8/:16/:24

3-, 8-, 16-, or 24-bit length

Note:

General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).

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