H8SLASH3021 datasheet(18/712 Pages) RENESAS

18 / 712 page

Rev.2.00 Mar. 22, 2007 Page xviii of xxiv

REJ09B0352-0200

9.1.1

Features................................................................................................................ 287

9.1.2

Block Diagram..................................................................................................... 288

9.1.3

Pin Configuration................................................................................................. 289

9.1.4

9.2

Register Descriptions ........................................................................................................ 291

9.2.1

Port A Data Direction Register (PADDR) ........................................................... 291

9.2.2

Port A Data Register (PADR).............................................................................. 291

9.2.3

Port B Data Direction Register (PBDDR) ........................................................... 292

9.2.4

Port B Data Register (PBDR) .............................................................................. 292

9.2.5

Next Data Register A (NDRA) ............................................................................ 293

9.2.6

Next Data Register B (NDRB)............................................................................. 295

9.2.7

Next Data Enable Register A (NDERA).............................................................. 297

9.2.8

Next Data Enable Register B (NDERB) .............................................................. 298

9.2.9

TPC Output Control Register (TPCR) ................................................................. 299

9.2.10 TPC Output Mode Register (TPMR) ................................................................... 302

9.3

Operation .......................................................................................................................... 305

9.3.1

Overview.............................................................................................................. 305

9.3.2

Output Timing...................................................................................................... 306

9.3.3

Normal TPC Output............................................................................................. 307

9.3.4

Non-Overlapping TPC Output ............................................................................. 309

9.4

Usage Notes ...................................................................................................................... 312

9.4.1

Operation of TPC Output Pins ............................................................................. 312

9.4.2

Note on Non-Overlapping Output........................................................................ 312

Section 10 Watchdog Timer............................................................................................. 315

10.1

Overview........................................................................................................................... 315

10.1.1 Features................................................................................................................ 315

10.1.2 Block Diagram..................................................................................................... 316

10.1.3 Pin Configuration................................................................................................. 316

10.1.4 Register Configuration......................................................................................... 317

10.2

Register Descriptions ........................................................................................................ 318

10.2.1 Timer Counter (TCNT)........................................................................................ 318

10.2.2 Timer Control/Status Register (TCSR)................................................................ 319

10.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 321

10.2.4 Notes on Register Access..................................................................................... 323

10.3

Operation .......................................................................................................................... 325

10.3.1 Watchdog Timer Operation ................................................................................. 325

10.3.2 Interval Timer Operation ..................................................................................... 326

10.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 327

10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 328

10.4

Interrupts ........................................................................................................................... 329

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