H8SLASH3021 datasheet(84/712 Pages) RENESAS

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3. MCU Operating Modes

Rev.2.00 Mar. 22, 2007 Page 60 of 684

REJ09B0352-0200

3.3

System Control Register (SYSCR)

SYSCR is an 8-bit register that controls the operation of the H8/3022 Group.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

—

Software standby

Enables transition to software standby mode

User bit enable

Selects whether to use UI bit in CCR

as a user bit or an interrupt mask bit

NMI edge select

Selects the valid edge

of the NMI input

Reserved bit

RAM enable

Enables or

disables

on-chip RAM

Standby timer select 2 to 0

These bits select the waiting time at

recovery from software standby mode

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further

information about software standby mode see section 17, Power-Down State.)

When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear

this bit, write 0.

Bit7

SSBY

Description

SLEEP instruction causes transition to sleep mode

(Initial value)

SLEEP instruction causes transition to software standby mode

Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU

and on-chip supporting modules wait for the internal clock oscillator to settle when software

standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at

least 7 ms at the system clock rate. For further information about waiting time selection, see

section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode.

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