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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3021 数据表(PDF) 85 Page - Renesas Technology Corp |
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H8/3021 数据表(HTML) 85 Page - Renesas Technology Corp |
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85 / 712 page  3. MCU Operating Modes Rev.2.00 Mar. 22, 2007 Page 61 of 684 REJ09B0352-0200 Bit6 STS2 Bit5 STS1 Bit4 STS0 Description 0 0 0 Waiting time = 8,192 states (Initial value) 0 0 1 Waiting time = 16,384 states 0 1 0 Waiting time = 32,768 states 0 1 1 Waiting time = 65,536 states 1 0 0 Waiting time = 131,072 states 1 0 1 Waiting time = 1,024 states 1 1 — Illegal setting Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as an interrupt mask bit 1 UI bit in CCR is used as a user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input. Bit2 NMIEG Description 0 An interrupt is requested at the falling edge of NMI (Initial value) 1 An interrupt is requested at the rising edge of NMI Bit 1—Reserved: This bit cannot be modified and is always read as 1. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by the rising edge of the RES signal. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled (Initial value) |
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