H8SLASH3021 datasheet(65/712 Pages) RENESAS

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2. CPU

Rev.2.00 Mar. 22, 2007 Page 41 of 684

REJ09B0352-0200

Finally, the CPU writes this value (H'FE) back to PADDR to complete the BCLR instruction.

As a result, PA0DDR is cleared to 0, making PA0 an input pin. In addition, PA7DDR and

PA6DDR are set to 1, making PA7 and PA6 output pins.

The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling

routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead

of time.

2.7

Addressing Modes and Effective Address Calculation

2.7.1

Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses

a subset of these addressing modes. Arithmetic and logic instructions can use the register direct

and immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit manipulation instructions use register direct, register

indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,

BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit

number in the operand.

Table 2.11

Addressing Modes

No.

Addressing Mode

Symbol

@ERn

@(d:16, ERn)/@d:24, ERn)

@ERn+

@–ERn

Absolute address

@aa:8/@aa:16/@aa:24

Immediate

#xx:8/#xx:16/#xx:32

Program-counter relative

@(d:8, PC)/@(d:16, PC)

Memory indirect

@@aa:8

1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit

R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit

registers.

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