H8SLASH3021 datasheet(61/712 Pages) RENESAS

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2. CPU

Rev.2.00 Mar. 22, 2007 Page 37 of 684

REJ09B0352-0200

Table 2.9

System Control Instructions

Instruction

Size*

Function

TRAPA

—

Starts trap-instruction exception handling

RTE

—

Returns from an exception-handling routine

SLEEP

—

Causes a transition to the power-down state

LDC

B/W

(EAs)

→ CCR

Moves the source operand contents to the condition code register. The

condition code register size is one byte, but in transfer from memory,

data is read by word access.

STC

B/W

CCR

→ (EAd)

Transfers the CCR contents to a destination location. The condition

code register size is one byte, but in transfer to memory, data is written

by word access.

ANDC

CCR

∧ #IMM → CCR

Logically ANDs the condition code register with immediate data.

ORC

CCR

∨ #IMM → CCR

Logically ORs the condition code register with immediate data.

XORC

CCR

⊕ #IMM → CCR

Logically exclusive-ORs the condition code register with immediate

data.

NOP

—

PC + 2

→ PC

Only increments the program counter.

Note:

Size refers to the operand size.

B: Byte

W: Word

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