H8SLASH3021 datasheet(87/712 Pages) RENESAS

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3. MCU Operating Modes

Rev.2.00 Mar. 22, 2007 Page 63 of 684

REJ09B0352-0200

3.5

Pin Functions in Each Operating Mode

The pin functions of ports 1 to 3, port 5 and port A vary depending on the operating mode. Table

3.3 indicates their functions in each operating mode.

Table 3.3

Pin Functions in Each Mode

Port

Mode 1

Mode 2*

Mode 3

Mode 4*

Mode 5

Mode 6

Mode 7

Port 1

7 to A0

—

7 to A0

—

7 to P10*

7 to P10

Port 2

15 to A8

—

15 to A8

—

7 to P20*

7 to P20

Port 3

7 to D0

—

7 to D0

—

7 to D0

7 to P30

Port 5

19 to A16

—

19 to A16

—

3 to P50*

3 to P50

Port A

7 to PA4

—

6 to PA4*

—

7 to PA4

6 to PA4*

7 to PA4

Notes: 1. H8/3022 Group cannot be used in these modes.

2. Initial state. These pins become address output pins when the corresponding bits in the

data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.

3. Initial state A

20 is always an address output pin. PA6 to PA4 are switched over to A23 to

21 output by writing 0 in bits 7 to 5 of ADRCR.

3.6

Memory Map in Each Operating Mode

Figure 3.1 shows a memory map of the H8/3022. Figure 3.2 shows a memory map of the H8/3021.

Figure 3.3 shows a memory map of the H8/3020. The address space is divided into eight areas.

Modes 1, 3, 5, and 6 are the 8-bit bus mode.

The address locations of the on-chip RAM and internal I/O registers differ between the 1-Mbyte

modes (modes 1, 5, and 7) and 16-Mbyte modes (mode 3 and 6). The address range specifiable by

the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs.

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