H8SLASH3021 datasheet(25/712 Pages) RENESAS

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1. Overview

Rev.2.00 Mar. 22, 2007 Page 1 of 684

REJ09B0352-0200

Section 1 Overview

1.1

Overview

The H8/3022 Group comprises microcomputers (MCUs) that integrate system supporting

functions together with an H8/300H CPU core featuring an original Renesas Technology

architecture.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,

enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit

(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial

communication interface (SCI), an A/D converter, I/O ports, and other facilities.

The H8/3022 Group consists of four models: the H8/3022 with 256 kbytes of ROM and 8 kbytes

of RAM, the H8/3021 with 192 kbytes of ROM and 8 kbytes of RAM, and the H8/3020 with 128

kbytes of ROM and 4 kbytes of RAM.

The five MCU operating modes offer a choice of expanded mode, single-chip mode and address

space size.

In addition to the masked-ROM version of the H8/3022 Group, an F-ZTAT* version with an on-

chip flash memory that can be freely programmed and reprogrammed by the user after the board is

installed is also available. This version enables users to respond quickly and flexibly to changing

application specifications, growing production volumes, and other conditions.

Table 1.1 summarizes the features of the H8/3022 Group.

Note: * F-ZTAT (Flexible ZTAT) is a trademark of Renesas Technology Corp.

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