H8SLASH3021 datasheet(101/712 Pages) RENESAS

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4. Exception Handling

Rev.2.00 Mar. 22, 2007 Page 77 of 684

REJ09B0352-0200

4.4

Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is

set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1

in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a

start address from a vector table entry corresponding to a vector number from 0 to 3, which is

specified in the instruction code.

4.5

Stack Status after Exception Handling

Figure 4.4 shows the stack after completion of trap instruction exception handling and interrupt

exception handling.

SP-4

SP-3

SP-2

SP-1

SP (ER7)

SP+1

SP+2

SP+3

SP+4

Before exception handling

After exception handling

CCR

Even address

Save on stack

Legend

PCE:

PCH:

PCL:

CCR:

SP:

Notes:

PC indicates the address of the first instruction that will be executed after return.

Saving and restoring of registers must be conducted at even addresses in word-size

or longword-size units.

Bits 23 to 16 of program counter (PC)

Bits 15 to 8 of program counter (PC)

Bits 7 to 0 of program counter (PC)

Condition code register

Stack pointer

Stack area

Figure 4.4 Stack after Completion of Exception Handling (Advanced Mode)

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