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H8/3028F 数据表(PDF) 332 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 332 Page - Renesas Technology Corp |
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332 / 923 page ![]() Rev. 2.00, 09/03, page 302 of 890 Pin Pin Functions and Selection Method Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows. PB4DDR 0 1 1 NDER12 — 0 1 PB4 input PB4 output TP12 output PB4/TP12/ UCAS Pin function UCAS output* Note: * UCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and regardless of bits NDER12 and PB4DDR. For details, see section 6, Bus Controller. The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB3DDR select the pin function as follows. DRAM interface settings (1) in table below (2) in table below OIS3/2 and OS1/0 All 0 Not all 0 — CS4E 0 1 — — PB3DDR 0 1 1 — — — NDER11 — 0 1 — — — PB3 input PB3 output TP11 output CS4 output TMIO3 output CS4 output* 3 TMIO3 input* 1 Pin function DREQ1 input*2 Notes: 1. TMIO3 input when CCLR1 = CCLR0 = 1. 2. When an external request is specified as a DMAC activation source, DREQ1 input regardless of bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB3DDR. 3. CS4 is output as RAS4. DRAM interface settings (1) (2) (1) DRAS2 0 1 DRAS1 01 01 PB3/TP11/ TMIO3/ DREQ1/CS4 DRAS0 0101 0101 |
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