H8SLASH3028F datasheet(329/923 Pages) RENESAS

329 / 923 page

Rev. 2.00, 09/03, page 299 of 890

8.12.2

Table 8.22 summarizes the registers of port B.

Table 8.22 Port B Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'EE00A

Port B data direction register

PBDDR

H'00

H'FFFDA

Port B data register

PBDR

R/W

H'00

Note: * Lower 20 bits of the address in advanced mode.

Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select

input or output for each pin in port B. When pins are used for TPC output, the corresponding

PBDDR bits must also be set.

Bit

Initial value

Read/Write

PB DDR

Port B data direction 7 to 0

These bits select input or output for port B pins

PB DDR

The pin functions that can be selected for port B differ between modes 1 to 5, and modes 6 and 7.

For the method of selecting the pin functions, see tables 8.23 and 8.24.

When port B functions as an input/output port, a pin in port B becomes an output port if the

corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0.

PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.

PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting. Therefore, if a transition is made to software standby mode while

port B is functioning as an input/output port and a PBDDR bit is set to 1, the corresponding pin

maintains its output state.

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