 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
H8/3028F 数据表(PDF) 354 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8/3028F 数据表(HTML) 354 Page - Renesas Technology Corp |
|
|
354 / 923 page  Rev. 2.00, 09/03, page 324 of 890 9.2.5 Timer Interrupt Status Register B (TISRB) TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture and enables or disables GRB compare match and input capture interrupt requests. 7 — 1 — Bit Initial value Read/Write 6 IMIEB2 0 R/W 5 IMIEB1 0 R/W 4 IMIEB0 0 R/W 3 — 1 — 2 IMFB2 0 R/(W) * 1 IMFB1 0 R/(W) * 0 IMFB0 0 R/(W) * Reserved bit Reserved bit Input capture/compare match interrupt enable B2 to B0 These bits enable or disable interrupts by the IMFB flags Input capture/compare match flags B2 to B0 Status flags indicating GRB compare match or input capture Note: * Only 0 can be written, to clear the flag. TISRB is initialized to H'88 by a reset and in standby mode. Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables the interrupt requested by the IMFB2 when IMFB2 flag is set to 1. Bit 6 IMIEB2 Description 0 IMIB2 interrupt requested by IMFB2 flag is disabled (Initial value) 1 IMIB2 interrupt requested by IMFB2 flag is enabled |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
