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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3028F 数据表(PDF) 357 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 357 Page - Renesas Technology Corp |
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357 / 923 page  Rev. 2.00, 09/03, page 327 of 890 9.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests. 7 — 1 — Bit Initial value Read/Write 6 OVIE2 0 R/W 5 OVIE1 0 R/W 4 OVIE0 0 R/W 3 — 1 — 2 OVF2 0 R/(W) * 1 OVF1 0 R/(W) * 0 OVF0 0 R/(W) * Reserved bit Reserved bit Overflow interrupt enable 2 to 0 These bits enable or disable interrupts by the OVF flags Overflow flags 2 to 0 Status flags indicating interrupts by OVF flags Note: * Only 0 can be written, to clear the flag. TISRC is initialized to H'88 by a reset and in standby mode. Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the OVF2 when OVF2 flag is set to 1. Bit 6 OVIE2 Description 0 OVI2 interrupt requested by OVF2 flag is disabled (Initial value) 1 OVI2 interrupt requested by OVF2 flag is enabled Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the OVF1 when OVF1 flag is set to 1. Bit 5 OVIE1 Description 0 OVI1 interrupt requested by OVF1 flag is disabled (Initial value) 1 OVI1 interrupt requested by OVF1 flag is enabled |
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