H8SLASH3028F datasheet(362/923 Pages) RENESAS

362 / 923 page

Rev. 2.00, 09/03, page 332 of 890

Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is

cleared.

Bit 6

CCLR1

Bit 5

CCLR0

Description

16TCNT is not cleared

(Initial value)

16TCNT is cleared by GRA compare match or input capture*

16TCNT is cleared by GRB compare match or input capture*

Synchronous clear: 16TCNT is cleared in synchronization with other

synchronized timers*

Notes: 1. 16TCNT is cleared by compare match when the general register functions as an output

compare register, and by input capture when the general register functions as an input

capture register.

2. Selected in TSNC.

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input

edges when an external clock source is used.

Bit 4

CKEG1

Bit 3

CKEG0

Description

Count rising edges

(Initial value)

Count falling edges

—

Count both edges

When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored.

Phase counting takes precedence.

Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock

source.

Bit 2

TPSC2

Bit 1

TPSC1

Bit 0

TPSC0

Function

Internal clock:

(Initial value)

Internal clock:

φ/2

Internal clock:

φ/4

Internal clock:

φ/8

External clock A: TCLKA input

External clock B: TCLKB input

External clock C: TCLKC input

External clock D: TCLKD input

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