H8SLASH3028F datasheet(370/923 Pages) RENESAS

370 / 923 page

Rev. 2.00, 09/03, page 340 of 890

9.4

Operation

9.4.1

Overview

A summary of operations in the various modes is given below.

Normal Operation: Each channel has a timer counter and general registers. The timer counter

counts up, and can operate as a free-running counter, periodic counter, or external event counter.

GRA and GRB can be used for input capture or output compare.

Synchronous Operation: The timer counters in designated channels are preset synchronously.

Data written to the timer counter in any one of these channels is simultaneously written to the

timer counters in the other channels as well. The timer counters can also be cleared synchronously

if so designated by the CCLR1 and CCLR0 bits in the TCRs.

PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare

match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending

on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB

automatically become output compare registers.

Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and

TCLKB is detected and 16TCNT2 counts up or down accordingly. When phase counting mode is

selected TCLKA and TCLKB become clock input pins and 16TCNT2 operates as an up/down-

counter.

9.4.2

Basic Functions

Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register (TSTR),

the timer counter (16TCNT) in the corresponding channel starts counting. The counting can be

free-running or periodic.

• Sample setup procedure for counter

Figure 9.12 shows a sample procedure for setting up a counter.

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