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H8/3028F 数据表(PDF) 373 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 373 Page - Renesas Technology Corp |
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373 / 923 page ![]() Rev. 2.00, 09/03, page 343 of 890 • 16TCNT count timing Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock ( φ) or one of three internal clock sources obtained by prescaling the system clock ( φ/2, φ/4, φ/8). Figure 9.15 shows the timing. φ Internal clock 16TCNT input clock 16TCNT N – 1 N N + 1 Figure 9.15 Count Timing for Internal Clock Sources External clock source The external clock pin (TCLKA to TCLKD) can be selected by bits TPSC2 to TPSC0 in 16TCR, and the detected edge by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 9.16 shows the timing when both edges are detected. φ External clock input 16TCNT input clock 16TCNT N – 1 N N + 1 Figure 9.16 Count Timing for External Clock Sources (when Both Edges are Detected) |
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