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H8/3028F 数据表(PDF) 376 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 376 Page - Renesas Technology Corp |
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376 / 923 page ![]() Rev. 2.00, 09/03, page 346 of 890 • Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB). When 16TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 9.20 shows the output compare timing. N + 1 N N φ 16TCNT input clock 16TCNT GR Compare match signal TIOCA, TIOCB Figure 9.20 Output Compare Output Timing Input Capture Function: The 16TCNT value can be transferred to a general register when an input edge is detected at an input capture input/output compare pin (TIOCA or TIOCB). Rising- edge, falling-edge, or both-edge detection can be selected. The input capture function can be used to measure pulse width or period. |
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