H8SLASH3028F datasheet(379/923 Pages) RENESAS

379 / 923 page

Rev. 2.00, 09/03, page 349 of 890

Setup for synchronization

Synchronous preset

Set the SYNC bits to 1 in TSNC for the channels to be synchronized.

When a value is written in 16TCNT in one of the synchronized channels, the same value is

simultaneously written in 16TCNT in the other channels.

Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture.

Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously.

Set the STR bits in TSTR to 1 to start the synchronized counters.

Select synchronization

Synchronous preset

Write to 16TCNT

Synchronous clear

Clearing

synchronized to this

channel?

Select counter clear source

Start counter

Counter clear

Synchronous clear

Start counter

Select counter clear source

Yes

Figure 9.24 Setup Procedure for Synchronization (Example)

Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1,

and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing

by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The

timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by

compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1,

and TIOCA2. For further information on PWM mode, see section 9.4.4, PWM Mode.

H8/3028F 数据表(PDF) 379 Page - Renesas Technology Corp