H8SLASH3028F datasheet(412/923 Pages) RENESAS

412 / 923 page

Rev. 2.00, 09/03, page 382 of 890

Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT

clearing source. Compare match A or B, or input capture B, can be selected as the clearing source.

Bit 4

CCLR1

Bit 3

CCLR0

Description

Clearing is disabled

(Initial value)

Cleared by compare match A

Cleared by compare match B/input capture B

Cleared by input capture B

Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0

and 8TCNT2 are not cleared by compare match B.

Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to

8TCNT is an internal or external clock.

Three internal clocks can be selected, all divided from the system clock (

φ): φ/8, φ/64, and φ/8192.

The rising edge of the selected internal clock triggers the count.

When use of an external clock is selected, three types of count can be selected: at the rising edge,

the falling edge, and both rising and falling edges.

When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded.

The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1 and

8TCR3 are set.

H8/3028F 数据表(PDF) 412 Page - Renesas Technology Corp