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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3028F 数据表(PDF) 413 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 413 Page - Renesas Technology Corp |
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413 / 923 page  Rev. 2.00, 09/03, page 383 of 890 Bit 2 CSK2 Bit 1 CSK1 Bit 0 CSK0 Description 0 0 0 Clock input disabled (Initial value) 1 Internal clock, counted on falling edge of φ/8 1 0 Internal clock, counted on falling edge of φ/64 1 Internal clock, counted on falling edge of φ/8192 1 0 0 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow signal* 1 Channel 1 (compare match count mode): Count on 8TCNT0 compare match A* 1 Channel 2 (16-bit count mode): Count on 8TCNT3 overflow signal* 2 Channel 3 (compare match count mode): Count on 8TCNT2 compare match A* 2 1 External clock, counted on rising edge 1 0 External clock, counted on falling edge 1 External clock, counted on both rising and falling edges Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the 8TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. 2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the 8TCNT2 compare match signal, no incrementing clock is generated. Do not use this setting. |
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