H8SLASH3028F datasheet(416/923 Pages) RENESAS

416 / 923 page

Rev. 2.00, 09/03, page 386 of 890

Bit 4—A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D

control register (ADCR), enables or disables A/D converter start requests by compare match A or

an external trigger.

TRGE*

Bit 4

ADTE

Description

A/D converter start requests by compare match A or external trigger pin

(

ADTRG) input are disabled

(Initial value)

A/D converter start requests by compare match A or external trigger pin

(

ADTRG) input are disabled

A/D converter start requests by external trigger pin (

ADTRG) input are

enabled, and A/D converter start requests by compare match A are disabled

A/D converter start requests by compare match A are enabled, and A/D

converter start requests by external trigger pin (

ADTRG) input are disabled

Note: * TRGE is bit 7 of the A/D control register (ADCR).

Bit 4—Reserved (In 8TCSR1): This bit is a reserved bit, but can be read and written.

Bit 4—Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of

TCORB1 and TCORB3.

Bit 4

ICE

Description

TCORB1 and TCORB3 are compare match registers

(Initial value)

TCORB1 and TCORB3 are input capture registers

When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB

registers in channels 0 to 3 is as shown in the tables below.

H8/3028F 数据表(PDF) 416 Page - Renesas Technology Corp