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H8/3028F 数据表(PDF) 490 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 490 Page - Renesas Technology Corp |
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490 / 923 page ![]() Rev. 2.00, 09/03, page 460 of 890 13.2.6 Serial Control Register (SCR) SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. Bit 7 6 5 4 32 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value Read/Write R/W 0 00 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Transmit-end interrupt enable Enables or disables transmit-end interrupts (TEI) Multiprocessor interrupt enable Enables or disables multiprocessor interrupts Receive enable Enables or disables the receiver Transmit enable Enables or disables the transmitter Receive interrupt enable Enables or disables receive-data-full interrupts (RXI) and receive-error interrupts (ERI) Transmit interrupt enable Enables or disables transmit-data-empty interrupts (TXI) Clock enable 1/0 These bits select the SCI clock source The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby mode. |
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