H8SLASH3028F datasheet(495/923 Pages) RENESAS

495 / 923 page

Rev. 2.00, 09/03, page 465 of 890

13.2.7

Serial Status Register (SSR)

SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the

operating status of the SCI.

Initial value

Read/Write

RR/W

Bit

Multiprocessor bit

transfer

Value of multiprocessor

bit to be transmitted

R/(W)*1

TDRE

RDRF

ORER

FER/ERS

PER

TEND

MPB

MPBT

Multiprocessor bit

Stores the received

multiprocessor bit value

Transmit end*2

Status flag indicating end of

transmission

Parity error

Status flag indicating detection

of a receive parity error

Framing error (FER)/Error signal status (ERS)*2

Status flag indicating detection of a receive framing

error, or flag indicating detection of an error signal

Overrun error

Status flag indicating detection

of a receive overrun error

Receive data register full

Status flag indicating that data has been received

and stored in RDR

Transmit data register empty

Status flag indicating that transmit data has been transferred from

TDR into TSR and new data can be written in TDR

Notes: 1. Only 0 can be written, to clear the flag.

2. Function differs between the normal serial communication interface and the smart card interface.

The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,

and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1.

The TEND and MPB flags are read-only bits that cannot be written.

SSR is initialized to H'84 by a reset and in standby mode.

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