H8SLASH3028F datasheet(523/923 Pages) RENESAS

523 / 923 page

Rev. 2.00, 09/03, page 493 of 890

TEND = 1

Read TEND flag in SSR

Yes

<End>

Clear TE bit to 0 in SCR

Clear DR bit to 0 and set DDR to 1

(2)

(1)

Initialize

(3)

(4)

(1)

(2)

(3)

(4)

TDRE = 1

All data transmitted?

Read TDRE flag in SSR

Start transmitting

Write transmit data in TDR

and set MPBT bit in SSR

Clear TDRE flag to 0

Output break signal?

SCI initialization:

the transmit data output function of the TxD pin

is selected automatically.

SCI status check and transmit data write:

read SSR, check that the TDRE flag is 1, then

write transmit data in TDR. Also set the MPBT

flag to 0 or 1 in SSR. Finally, clear the TDRE

flag to 0.

To continue transmitting serial data:

after checking that the TDRE flag is 1,

indicating that data can be written, write data

in TDR, then clear the TDRE flag to 0. When

the DMAC is activated by a transmit-data-

empty interrupt request (TXI) to write data in

TDR, the TDRE flag is checked and cleared

automatically.

To output a break signal at the end of serial

transmission:

set the DDR bit to 1 and clear the DR bit to 0,

then clear the TE bit to 0 in SCR.

Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data

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