H8SLASH3028F datasheet(607/923 Pages) RENESAS

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Rev. 2.00, 09/03, page 577 of 890

18.3

Flash Memory Version Register Description

18.3.1

Flash Memory Control Register 1 (FLMCR1)

Bit

654321

FWE

SWE

ESU

PSU

Initial value

—*

000000

Read/Write

R/W

Note: * Determined by the state of the FWE pin.

FLMCR1 is an 8-bit register used for flash memory operating mode control.

Program-verify mode or erase-verify mode for addresses H'00000 to H'5FFFF is entered by setting

the SWE bit when FWE = 1, then setting the PV or EV bit. Program mode for addresses H'00000

to H'5FFFF is entered by setting the SWE bit when FWE = 1, then setting the PSU bit, and finally

setting the P bit. Erase mode for addresses H'00000 to H'5FFFF is entered by setting the SWE bit

when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a

reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a

high level is input to the FWE pin, and H'00 when a low level is input. In mode 6 the FWE pin

must be fixed low since flash memory on-board programming modes are not supported. When the

on-chip flash memory is disabled, a read access to this register will return H'00, and writes are

invalid.

When setting bits 6 to 0 in this register, one bit must be set one at a time. Writes to the SWE bit in

FLMCR1 are enabled only when FWE = 1; writes to bits ESU, PSU, EV, and PV only when FWE

= 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to

the P bit only when FWE = 1, SWE = 1, and PSU = 1.

Notes: 1. The programming and erase flowcharts must be followed when setting the bits in this

2. Transitions are made to program mode, erase mode, program-verify mode, and erase-

verify mode according to the settings in this register. When reading flash memory as

normal on-chip ROM, bits 6 to 0 in this register must be cleared.

Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory

programming/erasing.

Bit 7

FWE

Description

When a low level is input to the FWE pin (hardware-protected state)

When a high level is input to the FWE pin

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