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H8/3028F 数据表(PDF) 660 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 660 Page - Renesas Technology Corp |
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660 / 923 page  Rev. 2.00, 09/03, page 630 of 890 VCC STBY EXTAL φ (internal or external) RES tDEXT VIH Figure 19.7 External Clock Output Settling Delay Timing 19.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate φ. 19.4 Prescalers The prescalers divide the system clock ( φ) to generate internal clocks (φ/2 to φ/4096). 19.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock ( φ). The frequency division ratio can be changed dynamically by modifying the value in DIVCR, as described below. Power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. The system clock generated by the frequency divider can be output at the φ pin. |
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