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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3028F 数据表(PDF) 659 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 659 Page - Renesas Technology Corp |
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659 / 923 page  Rev. 2.00, 09/03, page 629 of 890 Table 19.3 Clock Timing VCC = 3.0 V to 3.6 V Item Symbol Min Max Unit Test Conditions tEXL 0.3 0.7 tcyc φ ≥ 5 MHz External clock input low pulse width 60 — ns φ < 5 MHz tEXH 0.3 0.7 tcyc φ ≥ 5 MHz External clock input high pulse width 60 — ns φ < 5 MHz Figure 19.6 External clock rise time tEXr — 5 ns Figure 19.6 External clock fall time tEXf —5 ns 0.4 0.6 tcyc φ ≥ 5 MHz Clock low pulse width tCL 80 — ns φ < 5 MHz 0.4 0.6 tcyc φ ≥ 5 MHz Clock high pulse width tCH 80 — ns φ < 5 MHz Figure 21.11 External clock output settling delay time tDEXT* 500 — µs Figure 19.7 Note: * tDEXT includes a RES pulse width (tRESW). tRESW = 20 tcyc EXTAL tEXr tEXf VCC × 0.7 0.3 V tEXH tEXL VCC × 0.5 Figure 19.6 External Clock Input Timing |
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