H8SLASH3028F datasheet(797/923 Pages) RENESAS

797 / 923 page

Rev. 2.00, 09/03, page 767 of 890

BCR—Bus Control Register

H'EE024

Bus controller

Bit

Initial value

Read/Write

R/W

ICIS1

R/W

ICIS0

R/W

BROME

R/W

BRSTS1

R/W

BRSTS0

—

R/W

RDEA

R/W

WAITE

WAIT pin wait input is disabled

WAIT pin wait input is enabled

Burst cycle select 1

Burst access cycle comprises 2 states

Burst access cycle comprises 3 states

Burst ROM enable

Area 0 is a basic bus interface area

Area 0 is a burst ROM interface area

Idle cycle insertion 0

No idle cycle is inserted in case of consecutive external read and write cycles

Idle cycle is inserted in case of consecutive external read and write cycles

Idle cycle insertion 1

No idle cycle is inserted in case of consecutive external read cycles for different areas

Idle cycle is inserted in case of consecutive external read cycles for different areas

Burst cycle select 0

Max. 4 words in burst access

Max. 8 words in burst access

Area division unit select

Area divisions are as follows:

Areas 0 to 7 are the same size

(2 MB)

Wait pin enable

Area 0: 2 MB

Area 4: 1.93 MB

Area 1: 2 MB

Area 5: 4 kB

Area 2: 8 MB

Area 6: 23.75 kB

Area 3: 2 MB

Area 7: 22 B

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