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H8/3028F 数据表(PDF) 798 Page - Renesas Technology Corp

部件名 H8/3028F
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
PDF  923 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8/3028F 数据表(HTML) 798 Page - Renesas Technology Corp

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Rev. 2.00, 09/03, page 768 of 890
DRCRA—DRAM Control Register A
H'EE026
DRAM interface
DRAM area select
00
1
0
1
0
1
0
1
0
1
0
1
1
DRAS2 DRAS1 DRAS0
Area 5
Normal
Normal
Normal
Normal
Normal
DRAM space
(
CS
5)
Area 4
Normal
Normal
Normal
Normal
DRAM space
(
CS
4)
DRAM space
(
CS
4)
Area 3
Normal
Normal
DRAM space
(
CS
3)
DRAM space
(
CS
3)
DRAM space
(
CS
3)
Area 2
Normal
DRAM space
(
CS
2)
DRAM space
(
CS
2)
DRAM space
(
CS
2)
DRAM space
(
CS
2)
DRAM space(
CS
2)*
DRAM space(
CS
4)*
DRAM space(
CS
2)*
DRAM space(
CS
2)*
Note:
* A single CSn pin serves as a common RAS output pin for a number of
areas. Unused
CSn pins can be used as input/output ports.
7
DRAS2
0
R/W
6
DRAS1
0
R/W
5
DRAS0
0
R/W
4
—
1
—
3
BE
0
R/W
2
RDM
0
R/W
1
SRFMD
0
R/W
0
RFSHE
0
R/W
Bit
Initial value
Read/Write
Refresh pin enable
0
1
Self-refresh mode
RAS down mode
0
1
0
1
Burst access enable
0
1
RFSH pin refresh signal output is disabled
RFSH pin refresh signal output is enabled
DRAM self-refreshing is disabled in software standby mode
DRAM self-refreshing is enabled in software standby mode
DRAM interface: RAS up mode selected
DRAM interface: RAS down mode selected
Burst disabled (always full access)
DRAM space access performed in fast page mode



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