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H8/3028F 数据表(PDF) 799 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 799 Page - Renesas Technology Corp |
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799 / 923 page  Rev. 2.00, 09/03, page 769 of 890 DRCRB—DRAM Control Register B H'EE027 DRAM interface 7 MXC1 0 R/W 6 MXC0 0 R/W 5 CSEL 0 R/W 4 RCYCE 0 R/W 3 — 1 — 2 TPC 0 R/W 1 RCW 0 R/W 0 RLW 0 R/W Bit Initial value Read/Write Refresh cycle wait control 0 1 RAS-CAS wait TP cycle control 0 1 Refresh cycle enable 0 1 Wait state (T RW) insertion is disabled 1 wait state (T RW) is inserted 1-state precharge cycle is inserted 2-state precharge cycle is inserted Refresh cycles are disabled DRAM refresh cycles are enabled Multiplex control 1 and 0 00 1 0 1 1 MXC1 MXC0 Wait state (T rw) insertion is disabled 1 wait state (T rw) is inserted 0 1 CAS output pin select 0 1 PB4 and PB5 selected as UCAS and LCAS output pins HWR and LWR selected as UCAS and LCAS output pins Column address: 9 bits Compared address: Modes 1, 2 8-bit access space A 19 to A9 16-bit access space A 19 to A10 Modes 3, 4, 5 8-bit access space A 23 to A9 16-bit access space A 23 to A10 Column address: 10 bits Compared address: Modes 1, 2 8-bit access space A 19 to A10 16-bit access space A 19 to A11 Modes 3, 4, 5 8-bit access space A 23 to A10 16-bit access space A 23 to A11 Illegal setting Description Column address: 8 bits Compared address: Modes 1, 2 8-bit access space A 19 to A8 16-bit access space A 19 to A9 Modes 3, 4, 5 8-bit access space A 23 to A8 16-bit access space A 23 to A9 |
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