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H8/3028F 数据表(PDF) 121 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 121 Page - Renesas Technology Corp |
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121 / 923 page ![]() Rev. 2.00, 09/03, page 91 of 890 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ5 to IRQ0 interrupt requests. Bit Initial value Read/Write 7 — 0 R/W These bits enable or disable IRQ to IRQ interrupts 6 — 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W 50 IRQ to IRQ enable 50 Reserved bits IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable IRQ5 to IRQ0 interrupts. Bits 5 to 0 IRQ5E to IRQ0E Description 0IRQ5 to IRQ0 interrupts are disabled (Initial value) 1IRQ5 to IRQ0 interrupts are enabled |
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