H8SLASH3028F datasheet(124/923 Pages) RENESAS

124 / 923 page

Rev. 2.00, 09/03, page 94 of 890

Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).

IRQn

IRQnF

Note: n = 5 to 0

input pin

Figure 5.3 Timing of Setting of IRQnF

Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of

whether the corresponding pin is set for input or output. When using a pin for external interrupt

input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, SCI

input/output, or A/D external trigger input.

5.3.2

Internal Interrupts

Thirty-Six internal interrupts are requested from the on-chip supporting modules.

• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits

for enabling or disabling interrupts.

• Interrupt priority levels can be assigned in IPRA and IPRB.

• 16-bit timer, SCI, and A/D converter interrupt requests can activate the DMAC, in which case

no interrupt request is sent to the interrupt controller, and the I and UI bits are disregarded.

5.3.3

Interrupt Vector Table

Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the

default priority order, smaller vector numbers have higher priority. The priority of interrupts other

than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order

shown in table 5.3.

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