H8SLASH3028F datasheet(123/923 Pages) RENESAS

123 / 923 page

Rev. 2.00, 09/03, page 93 of 890

5.3

Interrupt Sources

The interrupt sources include external interrupts (NMI, IRQ0 to IRQ5) and 36 internal interrupts.

5.3.1

External Interrupts

There are seven external interrupts: NMI, and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and IRQ2

can be used to exit software standby mode.

NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I

and UI bits in CCR*. The NMIEG bit in SYSCR selects whether an interrupt is requested by the

rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector

number 7.

Note: * NMI input is sometimes disabled. For details see section 18.9, NMI Input Disabling

Conditions.

IRQ0 to IRQ5 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ5.

The IRQ0 to IRQ5 interrupts have the following features.

• ISCR settings can select whether an interrupt is requested by the low level of the input at pins

IRQ

0 to IRQ5, or by the falling edge.

• IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrupt priority levels can be

assigned by four bits in IPRA (IPRA7 to IPRA4).

• The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared

to 0 by software.

Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5.

input

Edge/level

sense circuit

IRQnSC

IRQnF

IRQnE

IRQn interrupt

request

Clear signal

IRQn

Note: n = 5 to 0

Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5

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