H8SLASH3028F datasheet(182/923 Pages) RENESAS

182 / 923 page

Rev. 2.00, 09/03, page 152 of 890

6.5.3

Address Multiplexing

When DRAM space is accessed, the row address and column address are multiplexed. The

address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the

number of bits in the DRAM column address. Table 6.6 shows the correspondence between the

settings of MXC1 and MXC0 and the address multiplexing method.

Table 6.6

Settings of Bits MXC1 and MXC0 and Address Multiplexing Method

DRCRB

Column

Address

Address Pins

MXC1 MXC0 Bits

A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Row

address

008 bits

A23 to A13 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8

19 bits

A23 to A13 A12 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

10 bits

A23 to A13 A12 A11 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

Illegal

setting

—

— ——— ——— ——— ———

Column

address

———

A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Note: * Row address bit A20 is not multiplexed in 1-Mbyte mode.

6.5.4

Data Bus

If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is

designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM

space. In 16-bit DRAM space,

× 16-bit organization DRAM can be connected directly.

In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM

space both the upper and lower halves of the data bus, D15 to D0, are enabled.

Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data

Size and Data Alignment.

6.5.5

Pins Used for DRAM Interface

Table 6.7 shows the pins used for DRAM interfacing and their functions.

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