H8SLASH3028F datasheet(183/923 Pages) RENESAS

183 / 923 page

Rev. 2.00, 09/03, page 153 of 890

Table 6.7

DRAM Interface Pins

With DRAM

Designated Name

I/O

Function

PB4

UCAS

Upper column

address strobe

Output

Upper column address strobe for DRAM

space access (when CSEL = 0 in DRCRB)

PB5

LCAS

Lower column

address strobe

Output

Lower column address strobe for DRAM

space access (when CSEL = 0 in DRCRB)

HWR

UCAS

Upper column

address strobe

Output

Upper column address strobe for DRAM

space access (when CSEL = 1 in DRCRB)

LWR

LCAS

Lower column

address strobe

Output

Lower column address strobe for DRAM

space access (when CSEL = 1 in DRCRB)

CS2

RAS2

Row address

strobe 2

Output

Row address strobe for DRAM space

access

CS3

RAS3

Row address

strobe 3

Output

Row address strobe for DRAM space

access

CS4

RAS4

Row address

strobe 4

Output

Row address strobe for DRAM space

access

CS5

RAS5

Row address

strobe 5

Output

Row address strobe for DRAM space

access

Write enable

Output

Write enable for DRAM space write

access*

P80

RFSH

Refresh

Output

Goes low in refresh cycle

A12 to A0 A12 to A0

Address

Output

Row address/column address multiplexed

output

D15 to D0 D15 to D0

Data

I/O

Data input/output pins

Note: * Fixed high in a read access.

6.5.6

Basic Timing

Figure 6.18 shows the basic access timing for DRAM space. The basic DRAM access timing is

four states: one precharge cycle (Tp) state, one row address output cycle (Tr) state, and two column

address output cycle (Tc1, Tc2) states. Unlike the basic bus interface, the corresponding bits in

ASTCR control only enabling or disabling of wait insertion between Tc1 and Tc2, and do not affect

the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states

cannot be inserted between Tc1 and Tc2 in the DRAM access cycle.

If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM

space when

HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is

inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle,

for details.

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