H8SLASH3028F datasheet(187/923 Pages) RENESAS

部件名	H8/3028F

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

187 / 923 page

Rev. 2.00, 09/03, page 157 of 890

When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only

UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0,

PB5 can be used as an input/output port.

Note that

RAS down mode cannot be used when a device other than DRAM is connected to

external space and

HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti)

is always inserted when an external access to other than DRAM space occurs after a DRAM space

access. For details, see section 6.9, Idle Cycle.

Table 6.8

CSEL Settings and

UCAS

UCAS and LCAS

LCAS

LCAS Output Pins

CSEL

UCAS

LCAS

0PB4

PB5

HWR

LWR

Figure 6.21 shows the control timing.

A23 to A0

CSn (RAS)

Tc1

Tc2

PB4 (UCAS)

PB5 (LCAS)

RD (WE)

Note: n = 2 to 5

Byte control

Row

Column

Figure 6.21 Control Timing (Upper-Byte Write Access When CSEL = 0)

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