H8SLASH3028F datasheet(188/923 Pages) RENESAS

188 / 923 page

Rev. 2.00, 09/03, page 158 of 890

6.5.10

Burst Operation

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a

row address for each access, a fast page mode is also provided which can be used when making a

number of consecutive accesses to the same row address. This mode enables fast (burst) access of

data by simply changing the column address after the row address has been output. Burst access

can be selected by setting the BE bit to 1 in DRCRA.

Burst Access (Fast Page Mode) Operation Timing: Figure 6.22 shows the operation timing for

burst access. When there are consecutive access cycles for DRAM space, the column address and

CAS signal output cycles (two states) continue as long as the row address is the same for

consecutive access cycles. In burst access, too, the bus cycle can be extended by inserting wait

states between Tc1 and Tc2. The wait state insertion method and timing are the same as for full

access: see section 6.5.8, Wait Control, for details.

The row address used for the comparison is determined by the bus width of the relevant area set in

bits MXC1 and MXC0 in BRCRB, and in ABWCR. Table 6.9 shows the compared row addresses

corresponding to the various settings of bits MXC1 and MXC0, and ABWCR.

A23 to A0

CSn (RAS)

Tc2

(

UCAS/LCAS)

PB4/PB5

RD (WE)

D15 to D0

(

UCAS/LCAS)

PB4/PB5

Tc2

Tc1

D15 to D0

RD (WE)

Note: n = 2 to 5

Read access

Write access

Row

Column 1

Column 2

High level

Figure 6.22 Operation Timing in Fast Page Mode

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