H8SLASH3028F datasheet(190/923 Pages) RENESAS

190 / 923 page

Rev. 2.00, 09/03, page 160 of 890

RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as

accesses are to the same row address, burst operation can be continued without interruption even if

accesses are not consecutive by holding the

RAS signal low.

• RAS Down Mode

To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM

space is interrupted and another space is accessed, the

RAS signal is held low during the

access to the other space, and burst access is performed if the row address of the next DRAM

space access is the same as the row address of the previous DRAM space access. Figure 6.23

shows an example of the timing in RAS down mode.

A23 to A0

CSn (RAS)

Tc2

(

UCAS/LCAS)

PB4/PB5

D15 to D0

Tc1

Tc2

Tc1

Note: n = 2 to 5

DRAM access

External space

access

Figure 6.23 Example of Operation Timing in RAS Down Mode (CSEL = 0)

When RAS down mode is selected, the conditions for an asserted

RASn signal to return to the

high level are as shown below. The timing in these cases is shown in figure 6.24.

 When DRAM space with a different row address is accessed

 Immediately before a CAS-before-RAS refresh cycle

 When the BE bit or RDM bit is cleared to 0 in DRCRA

 Immediately before release of the external bus

H8/3028F 数据表(PDF) 190 Page - Renesas Technology Corp