H8SLASH3028F datasheet(240/923 Pages) RENESAS

240 / 923 page

Rev. 2.00, 09/03, page 210 of 890

Repeat Mode: One byte or word is transferred per request. A designated number of these transfers

are executed. When the designated number of transfers are completed, the initial address and

counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit

address and one 8-bit address are specified. The transfer direction is determined automatically

from the activation source.

Normal Mode

• Auto-request

The DMAC is activated by register setup alone, and continues executing transfers until the

designated number of transfers have been completed. A CPU interrupt can be requested at

completion of the transfers. Both addresses are 24-bit addresses.

 Cycle-steal mode

The bus is released to another bus master after each byte or word is transferred.

 Burst mode

Unless requested by a higher-priority bus master, the bus is not released until the

designated number of transfers have been completed.

• External request

One byte or word is transferred per request. A designated number of these transfers are

executed. A CPU interrupt can be requested at completion of the designated number of

transfers. Both addresses are 24-bit addresses.

Block Transfer Mode: One block of a specified size is transferred per request. A designated

number of block transfers are executed. At the end of each block transfer, one address is restored

to its initial value. When the designated number of blocks have been transferred, a CPU interrupt

can be requested. Both addresses are 24-bit addresses.

H8/3028F 数据表(PDF) 240 Page - Renesas Technology Corp