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H8/3028F 数据表(PDF) 244 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 244 Page - Renesas Technology Corp |
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244 / 923 page ![]() Rev. 2.00, 09/03, page 214 of 890 Table 7.7 Register Functions in Idle Mode Function Register Activated by SCI 0 Receive- Data-Full Interrupt Other Activation Initial Setting Operation 23 0 MAR Destination address register Source address register Destination or source address Held fixed All 1s IOAR 23 0 7 Source address register Destination address register Source or destination address Held fixed 15 0 ETCR Transfer counter Number of transfers Decremented once per transfer until H'0000 is reached and transfer ends Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. MAR and IOAR are not incremented or decremented. Figure 7.4 illustrates how idle mode operates. Transfer 1 byte or word is transferred per request IOAR MAR Figure 7.4 Operation in Idle Mode |
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