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H8/3028F 数据表(PDF) 246 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 246 Page - Renesas Technology Corp |
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246 / 923 page ![]() Rev. 2.00, 09/03, page 216 of 890 7.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). At the end of the designated number of transfers, MAR and ETCRH are restored to their original values and operation continues. The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data- full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.8 indicates the register functions in repeat mode. Table 7.8 Register Functions in Repeat Mode Function Register Activated by SCI 0 Receive- Data-Full Interrupt Other Activation Initial Setting Operation Destination address register Source address register Destination or source start address Incremented or decremented at each transfer until ETCRH reaches H'0000, then restored to initial value Source address register Destination address register Source or destination address Held fixed Transfer counter Number of transfers Decremented once per transfer until H'0000 is reached, then reloaded from ETCRL Initial transfer count Number of transfers Held fixed Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register 23 0 MAR All 1s IOAR 23 0 70 ETCRH 7 70 ETCRL |
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