H8SLASH3028F datasheet(248/923 Pages) RENESAS

248 / 923 page

Rev. 2.00, 09/03, page 218 of 890

The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer

count is 255, obtained by setting both ETCRH and ETCRL to H'FF.

Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit

timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,

conversion-end interrupts from the A/D converter, and external request signals.

For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR).

Figure 7.7 shows a sample setup procedure for repeat mode.

Set source and

destination addresses

Set transfer count

Read DTCR

Set DTCR

Repeat mode

Set the source and destination addresses in MAR

and IOAR. The transfer direction is determined

automatically from the activation source.

Set the transfer count in both ETCRH and ETCRL.

Read DTCR while the DTE bit is cleared to 0.

Select byte size or word size with the DTSZ bit.

Set the DTE bit to 1 to enable the transfer.

•

Select the DMAC activation source with bits

DTS2 to DTS0.

Clear the DTIE bit to 0 and set the RPE bit to 1

to select repeat mode.

Select MAR increment or decrement with the DTID bit.

Set the DTCR bits as follows.

Figure 7.7 Repeat Mode Setup Procedure (Example)

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