H8SLASH3028F datasheet(249/923 Pages) RENESAS

249 / 923 page

Rev. 2.00, 09/03, page 219 of 890

7.4.5

Normal Mode

In normal mode the A and B channels are combined. One byte or word is transferred per request.

A designated number of these transfers are executed. Addresses are specified in MARA and

MARB. Table 7.9 indicates the register functions in I/O mode.

Table 7.9

Function

Initial Setting

Operation

MARA

Source address

Source start

address

Incremented or

decremented once per

transfer, or held fixed

MARB

Destination

address register

Destination start

address

Incremented or

decremented once per

transfer, or held fixed

ETCRA

Transfer counter

Number of

transfers

Decremented once per

transfer

Legend

MARA: Memory address register A

MARB: Memory address register B

ETCRA: Execute transfer count register A

The source and destination addresses are both 24-bit addresses. MARA specifies the source

address. MARB specifies the destination address. MARA and MARB can be independently

incremented, decremented, or held fixed as data is transferred.

The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by

1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer

ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer

count is 65,536, obtained by setting ETCRA to H'0000.

H8/3028F 数据表(PDF) 249 Page - Renesas Technology Corp

H8/3028F 数据表(HTML) 249 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载