H8SLASH3028F datasheet(252/923 Pages) RENESAS

252 / 923 page

Rev. 2.00, 09/03, page 222 of 890

7.4.6

Block Transfer Mode

In block transfer mode the A and B channels are combined. One block of a specified size is

transferred per request. A designated number of block transfers are executed. Addresses are

specified in MARA and MARB. The block area address can be either held fixed or cycled.

Table 7.10 indicates the register functions in block transfer mode.

Table 7.10 Register Functions in Block Transfer Mode

Function

Initial Setting

Operation

Source address

Source start

address

Incremented or

decremented once per

transfer, or held fixed

Destination

address register

Destination start

address

Incremented or

decremented once per

transfer, or held fixed

Block size counter

Block size

Decremented once per

transfer until H'00 is

reached, then reloaded

from ETCRL

Initial block size

Block size

Held fixed

Block transfer

counter

Number of block

transfers

Decremented once per

block transfer until H'0000

is reached and the

transfer ends

Legend

MARA:

Memory address register A

MARB:

Memory address register B

ETCRA: Execute transfer count register A

ETCRB: Execute transfer count register B

MARA

ETCRAH

ETCRAL

MARB

ETCRB

The source and destination addresses are both 24-bit addresses. MARA specifies the source

address. MARB specifies the destination address. MARA and MARB can be independently

incremented, decremented, or held fixed as data is transferred. One of these registers operates as a

block area register: even if it is incremented or decremented, it is restored to its initial value at the

end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or

destination.

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