H8SLASH3028F datasheet(256/923 Pages) RENESAS

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Rev. 2.00, 09/03, page 226 of 890

Figure 7.12 shows a sample setup procedure for block transfer mode.

10.

Block transfer mode

Set source address

Set destination address

Set block transfer count

Set block size

Set DTCRB (1)

Set DTCRA (1)

Read DTCRB

Set DTCRB (2)

Read DTCRA

Set DTCRA (2)

Block transfer mode

Set the source address in MARA.

Set the destination address in MARB.

Set the block transfer count in ETCRB.

Set the block size (number of bytes or words)

in both ETCRAH and ETCRAL.

Set the DTCRB bits as follows.

Set the DTCRA bits as follows.

•

Clear the DTME bit to 0.

Set the DAID and DAIDE bits to select whether

MARB is incremented, decremented, or held fixed.

Set or clear the TMS bit to make the block area

the source or destination.

Select the DMAC activation source with bits

DTS2B to DTS0B.

Clear the DTE to 0.

Select byte size or word size with the DTSZ bit.

Set the SAID and SAIDE bits to select whether

MARA is incremented, decremented, or held fixed.

Set or clear the DTIE bit to enable or disable the

CPU interrupt at the end of the transfer.

Set bits DTS2A to DTS0A all to 1 to select

block transfer mode.

Read DTCRB with DTME cleared to 0.

Set the DTME bit to 1 in DTCRB.

Read DTCRA with DTE cleared to 0.

Set the DTE bit to 1 in DTCRA to enable

the transfer.

Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU.

If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in

which case the transfer will not start.

Figure 7.12 Block Transfer Mode Setup Procedure (Example)

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