H8SLASH3028F datasheet(254/923 Pages) RENESAS

254 / 923 page

Rev. 2.00, 09/03, page 224 of 890

When activated by a transfer request, the DMAC executes a burst transfer. During the transfer

MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented.

When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The

memory address register of the block area is also restored to its initial value, and ETCRB is

decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request.

ETCRAH and ETCRAL should be initially set to the same value.

The above operation is repeated until ETCRB reaches H'0000, at which point the DTE bit is

cleared to 0 and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this

time.

Figure 7.11 shows examples of a block transfer with byte data size when the block area is the

destination. In (a) the block area address is cycled. In (b) the block area address is held fixed.

Transfers can be requested (activated) by compare match/input capture A interrupts from ITU

channels 0 to 2, by an A/D converter conversion-end interrupt, and by external request signals.

For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).

H8/3028F 数据表(PDF) 254 Page - Renesas Technology Corp