H8SLASH3028F datasheet(243/923 Pages) RENESAS

243 / 923 page

Rev. 2.00, 09/03, page 213 of 890

Figure 7.3 shows a sample setup procedure for I/O mode.

Set source and

destination addresses

Set transfer count

Read DTCR

Set DTCR

I/O mode

I/O mode setup

Set the source and destination addresses

in MAR and IOAR. The transfer direction is

determined automatically from the activation

source.

Set the transfer count in ETCR.

Read DTCR while the DTE bit is cleared to 0.

Set the DTCR bits as follows.

Select the DMAC activation source with bits

DTS2 to DTS0.

Set or clear the DTIE bit to enable or disable

the CPU interrupt at the end of the transfer.

Clear the RPE bit to 0 to select I/O mode.

Select MAR increment or decrement with the

DTID bit.

Select byte size or word size with the DTSZ bit.

Set the DTE bit to 1 to enable the transfer.

•

Figure 7.3 I/O Mode Setup Procedure (Example)

7.4.3

Idle Mode

Idle mode can be selected independently for each channel.

One byte or word is transferred at each transfer request in idle mode. A designated number of

these transfers are executed. One address is specified in the memory address register (MAR), the

other in the I/O address register (IOAR). The direction of transfer is determined automatically

from the activation source. The transfer is from the address specified in IOAR to the address

specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the

address specified in MAR to the address specified in IOAR otherwise.

Table 7.7 indicates the register functions in idle mode.

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