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H8/3028F 数据表(PDF) 283 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 283 Page - Renesas Technology Corp |
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283 / 923 page ![]() Rev. 2.00, 09/03, page 253 of 890 8.3 Port 2 8.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 8.2. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus output pins (A15 to A8). In mode 5 (expanded modes with on-chip ROM enabled), settings in the port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8) or generic input. In modes 6 and 7 (single-chip mode), port 2 is a generic input/output port. When DRAM is connected to areas 2 to 5, A12 to A8 output row and column addresses in read and write cycles. For details see section 6.5, DRAM Interface. Port 2 has software-programmable built-in pull-up transistors. Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a darlington transistor pair. Port 2 P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 P2 (input/output) P2 (input/output) P2 (input/output) P2 (input/output) P2 (input/output) P2 (input/output) P2 (input/output) P2 (input/output) 7 6 5 4 3 2 1 0 A (output) A (output) A (output) A (output) A (output) A (output) A (output) A (output) 15 14 13 12 11 10 9 8 Port 2 pins Modes 6 and 7 Modes 1 to 4 P2 (input)/A (output) P2 (input)/A (output) P2 (input)/A (output) P2 (input)/A (output) P2 (input)/A (output) P2 (input)/A (output) P2 (input)/A (output) P2 (input)/A (output) 7 6 5 4 3 2 1 0 Mode 5 15 14 13 12 11 10 9 8 Figure 8.2 Port 2 Pin Configuration |
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