H8SLASH3028F datasheet(284/923 Pages) RENESAS

284 / 923 page

Rev. 2.00, 09/03, page 254 of 890

8.3.2

Table 8.3 summarizes the registers of port 2.

Table 8.3

Port 2 Registers

Initial Value

Address*

Name

Abbreviation R/W Modes 1 to 4 Modes 5 to 7

H'EE001

Port 2 data direction register

P2DDR

H'FF

H'00

H'FFFD1

Port 2 data register

P2DR

R/W H'00

H'00

H'EE03C

Port 2 input pull-up MOS control

P2PCR

R/W H'00

H'00

Note: * Lower 20 bits of the address in advanced mode.

Port 2 Data Direction Register (P2DDR): P2DDR is an 8-bit write-only register that can select

input or output for each pin in port 2.

Bit

Modes

1 to 4

Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

Port 2 data direction 7 to 0

These bits select input or

output for port 2 pins

Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P2DDR values are fixed at 1.

Port 2 functions as an address bus.

Mode 5 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 2 is an input

port. A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set to 1, and

a generic input port if this bit is cleared to 0.

Modes 6 and 7 (Single-Chip Mode): Port 2 functions as an input/output port. A pin in port 2

becomes an output port if the corresponding P2DDR bit is set to 1, and an input port if this bit is

cleared to 0.

In modes 1 to 4, P2DDR bits are always read as 1, and cannot be modified.

In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when

read.

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